? semiconductor components industries, llc, 2016 january, 2016 ? rev. 10 1 publication order number: mc74hc73/d mc74hc73a dual j-k flip-flop with reset high?performance silicon?gate cmos the mc74hc73a is identical in pinout to the ls73. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. each flip?flop is negative?edge clocked and has an active?low asynchronous reset. the mc74hc73a is identical in function to the hc107, but has a different pinout. features ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices ? in compliance with the jedec standard no. 7.0 a requirements ? chip complexity: 92 fets or 23 equivalent gates ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these are pb?free devices pin assignment function table logic diagram pin 4 = v cc pin 11 = gnd reset 2 k2 clock 2 j2 reset 1 k1 clock 1 j1 q2 q2 q1 q1 14 1 3 2 7 5 10 6 12 13 9 8 11 12 13 14 8 9 10 5 4 3 2 1 7 6 k2 gnd q1 q1 j1 q2 q2 v cc k1 reset 1 clock 1 j2 reset 2 clock 2 inputs outputs reset clock j k q q lxxxlh h l l no change hlhlh hhlhl h h h toggle h l x x no change h h x x no change h x x no change www. onsemi.com marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb?free package tssop?14 dt suffix case 948g 14 1 soic?14 d suffix case 751a 14 1 hc73ag awlyww 1 14 hc 73a alyw 1 14 see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information (note: microdot may be in either location)
mc74hc73a www. onsemi.com 2 maximum ratings symbol parameter value unit v cc dc supply voltage (referenced to gnd) ? 0.5 to + 7.0 v v in dc input voltage (referenced to gnd) ? 1.5 to v cc + 1.5 v v out dc output voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air soic package? 500 mw t stg storage temperature ? 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds (psoic package) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ?derating ? soic package: ? 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ? 55 + 125 c t r , t f input rise and fall time v cc = 2.0 v (figure 1) v cc = 4.5 v v cc = 6.0 v 0 0 0 1000 500 400 ns functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recommended operating ranges limits may affect device reliability. dc electrical characteristics (voltages referenced to gnd) symbol parameter test conditions v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c v ih minimum high?level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 v v il maximum low?level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 v v oh minimum high?level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v ih or v il |i out | 4.0 ma |i out | 5.2 ma 4.5 6.0 3.98 5.48 3.84 5.34 3.70 5.20 v ol maximum low?level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 4.0 ma |i out | 5.2 ma 4.5 6.0 0.26 0.26 0.33 0.33 0.40 0.40 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 4 40 80 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc73a www. onsemi.com 3 ac electrical characteristics (c l = 50 pf, input t r = t f = 6 ns) symbol parameter v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c f max maximum clock frequency (50% duty cycle) (figures 1 and 4) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 mhz t plh , t phl maximum propagation delay, clock to q or q (figures 1 and 4) 2.0 4.5 6.0 125 25 21 155 31 26 190 38 32 ns t plh , t phl maximum propagation delay, reset to q or q (figures 2 and 4) 2.0 4.5 6.0 155 31 26 195 39 33 235 47 40 ns t tlh , t thl maximum output transition time, any output (figures 1 and 4) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns c in maximum input capacitance ? 10 10 10 pf c pd power dissipation capacitance (per flip?flop)* typical @ 25 c, v cc = 5.0 v pf 35 * used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . timing requirements (input t r = t f = 6 ns) symbol parameter v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c t su minimum setup time, j or k to clock (figure 3) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns t h minimum hold time, clock to j or k (figure 3) 2.0 4.5 6.0 3 3 3 3 3 3 3 3 3 ns t rec minimum recovery time, reset inactive to clock (figure 2) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns t w minimum pulse width, clock (figure 1) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns t w minimum pulse width, reset (figure 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns t r , t f maximum input rise and fall times (figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns
mc74hc73a www. onsemi.com 4 switching waveforms t su *includes all probe and jig capacitance c l * test point device under test output clock q or q 90% 90% 50% 10% t f t r v cc gnd t w 1/f max t plh t phl 90% 50% 10% t tlh t thl figure 1. figure 2. figure 3. figure 4. 50% 50% 50% 50% v cc v cc gnd gnd reset q q clock t plh t phl t rec t w valid 50% j or k clock v cc v cc gnd gnd t h expanded logic diagram reset k clock 2, 6 14, 7 3, 10 1, 5 cl cl cl cl cl cl cl cl cl cl cl q q 12, 9 13, 8 cl cl cl j
mc74hc73a www. onsemi.com 5 ordering information device package shipping ? mc74hc73adg soic?14 (pb?free) 55 units / rail mc74hc73adr2g soic?14 (pb?free) 2500 / tape & reel NLV74HC73ADR2G* soic?14 (pb?free) 2500 / tape & reel mc74hc73adtg tssop?14 (pb?free) 96 units / tube mc74hc73adtr2g tssop?14 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
mc74hc73a www. onsemi.com 6 package dimensions tssop?14 case 948g issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include damba r protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ?u? seating plane 0.10 (0.004) ?t? ??? ??? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ?v? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hc73a www. onsemi.com 7 package dimensions soic?14 nb case 751a?03 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a dim min max min max inches millimeters d 8.55 8.75 0.337 0.344 e 3.80 4.00 0.150 0.157 a 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 l 0.40 1.25 0.016 0.049 e 1.27 bsc 0.050 bsc a3 0.19 0.25 0.008 0.010 a1 0.10 0.25 0.004 0.010 m 0 7 0 7 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 6.50 14x 0.58 14x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74hc73/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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